// loopback: generated by xetal-fpga from an X_eTaL program; do not edit.
// Clocked: registers from reset, one stream item per clock.
module loopback (
  input  wire clk,
  input  wire rst,
  input  wire [15:0] in_c,
  output wire [15:0] out_line,
  output wire [63:0] out_lg,
  output wire [15:0] out_ct
);
  reg signed [15:0] n1;
  reg signed [15:0] n2;
  reg signed [15:0] n3;
  reg signed [15:0] n4;
  reg signed [15:0] n5;
  reg signed [15:0] n6;
  reg signed [15:0] n7;
  reg signed [15:0] n8;
  reg signed [15:0] n9;
  reg signed [15:0] n10;
  reg signed [15:0] n11;
  reg signed [15:0] n12;
  reg signed [15:0] n13;
  reg signed [15:0] n14;
  reg signed [15:0] n15;
  wire signed [15:0] n0 = in_c[15:0];
  wire signed [15:0] n16 = 16'sh0;
  wire signed [15:0] n17 = 16'sh1;
  wire signed [15:0] n18 = 16'sh2;
  wire signed [15:0] n19 = 16'sh8;
  wire signed [15:0] n20 = 16'sha;
  wire signed [15:0] n21 = 16'sh80;
  wire signed [15:0] n22 = 16'shff;
  wire signed [15:0] n23 = 16'sh200;
  wire signed [15:0] n24 = 16'sh2;
  wire signed [15:0] n25 = 16'sh3;
  wire signed [15:0] n26 = 16'sh0;
  wire signed [15:0] n27 = 16'sh1;
  wire signed [15:0] n28 = 16'sh2;
  wire signed [15:0] n29 = 16'sh3;
  wire signed [15:0] n30 = 16'sh4;
  wire signed [15:0] n31 = 16'sh5;
  wire signed [15:0] n32 = 16'sh6;
  wire signed [15:0] n33 = 16'sh7;
  wire signed [15:0] n34 = 16'sh8;
  wire signed [15:0] n35 = 16'sh9;
  wire signed [15:0] n36 = 16'sha;
  wire signed [15:0] n37 = 16'shb;
  wire signed [15:0] n38 = 16'shc;
  wire signed [15:0] n39 = 16'shd;
  wire signed [15:0] n40 = 16'she;
  wire signed [15:0] n41 = n4 & n17;
  wire n42 = n1 == n16;
  wire signed [15:0] n43 = n42 ? n17 : n41;
  wire n44 = n0 >= n16;
  wire n45 = n42 & n44;
  wire n46 = n2 > n16;
  wire n47 = n3 == n17;
  wire signed [15:0] n48 = n0 & n22;
  wire signed [15:0] n49 = n48 * n18;
  wire signed [15:0] n50 = n49 + n23;
  wire signed [15:0] n51 = n2 - n17;
  wire signed [15:0] n52 = n3 - n17;
  wire signed [15:0] n53 = n4 >>> 1;
  wire n54 = ~n47;
  wire n55 = n46 | n54;
  wire signed [15:0] n56 = {{15{1'b0}}, n55};
  wire signed [15:0] n57 = {{15{1'b0}}, n45};
  wire signed [15:0] n58 = n42 ? n57 : n56;
  wire signed [15:0] n59 = n45 ? n24 : n16;
  wire signed [15:0] n60 = n47 ? n16 : n24;
  wire signed [15:0] n61 = n46 ? n51 : n60;
  wire signed [15:0] n62 = n42 ? n59 : n61;
  wire signed [15:0] n63 = n45 ? n20 : n16;
  wire signed [15:0] n64 = n47 ? n16 : n52;
  wire signed [15:0] n65 = n46 ? n3 : n64;
  wire signed [15:0] n66 = n42 ? n63 : n65;
  wire signed [15:0] n67 = n45 ? n50 : n16;
  wire signed [15:0] n68 = n47 ? n16 : n53;
  wire signed [15:0] n69 = n46 ? n4 : n68;
  wire signed [15:0] n70 = n42 ? n67 : n69;
  wire n71 = n5 == n16;
  wire n72 = n43 == n16;
  wire n73 = n71 & n72;
  wire n74 = n5 == n18;
  wire n75 = n6 > n16;
  wire n76 = n7 == n17;
  wire signed [15:0] n77 = n8 >>> 1;
  wire signed [15:0] n78 = n43 * n21;
  wire signed [15:0] n79 = n77 + n78;
  wire signed [15:0] n80 = n17 - n43;
  wire signed [15:0] n81 = n18 * n80;
  wire signed [15:0] n82 = {{15{1'b0}}, n73};
  wire signed [15:0] n83 = n76 ? n18 : n17;
  wire signed [15:0] n84 = n75 ? n17 : n83;
  wire signed [15:0] n85 = n74 ? n81 : n84;
  wire signed [15:0] n86 = n71 ? n82 : n85;
  wire signed [15:0] n87 = n73 ? n25 : n16;
  wire signed [15:0] n88 = n6 - n17;
  wire signed [15:0] n89 = n76 ? n16 : n24;
  wire signed [15:0] n90 = n75 ? n88 : n89;
  wire signed [15:0] n91 = n74 ? n16 : n90;
  wire signed [15:0] n92 = n71 ? n87 : n91;
  wire signed [15:0] n93 = n73 ? n19 : n16;
  wire signed [15:0] n94 = n7 - n17;
  wire signed [15:0] n95 = n76 ? n16 : n94;
  wire signed [15:0] n96 = n75 ? n7 : n95;
  wire signed [15:0] n97 = n74 ? n16 : n96;
  wire signed [15:0] n98 = n71 ? n93 : n97;
  wire signed [15:0] n99 = n76 ? n16 : n79;
  wire signed [15:0] n100 = n75 ? n8 : n99;
  wire signed [15:0] n101 = n74 ? n16 : n100;
  wire signed [15:0] n102 = n71 ? n16 : n101;
  wire n103 = n5 == n17;
  wire n104 = ~n75;
  wire n105 = n103 & n104;
  wire n106 = n105 & n76;
  wire signed [15:0] n107 = {{15{1'b0}}, n106};
  wire signed [15:0] n108 = n106 ? n79 : n9;
  wire signed [15:0] n109 = 16'sh0;
  wire n110 = n15 == n109;
  wire signed [15:0] n111 = n110 ? n108 : n11;
  wire signed [15:0] n112 = 16'sh1;
  wire n113 = n15 == n112;
  wire signed [15:0] n114 = n113 ? n108 : n12;
  wire signed [15:0] n115 = 16'sh2;
  wire n116 = n15 == n115;
  wire signed [15:0] n117 = n116 ? n108 : n13;
  wire signed [15:0] n118 = 16'sh3;
  wire n119 = n15 == n118;
  wire signed [15:0] n120 = n119 ? n108 : n14;
  wire signed [15:0] n121 = n106 ? n111 : n11;
  wire signed [15:0] n122 = n106 ? n114 : n12;
  wire signed [15:0] n123 = n106 ? n117 : n13;
  wire signed [15:0] n124 = n106 ? n120 : n14;
  wire signed [15:0] n125 = n15 + n107;
  wire signed [15:0] n126 = 16'sh0;
  wire signed [15:0] n127 = 16'sh0;
  wire signed [15:0] n128 = 16'sh0;
  wire signed [15:0] n129 = 16'sh0;
  wire signed [15:0] n130 = 16'sh0;
  wire signed [15:0] n131 = 16'sh0;
  wire signed [15:0] n132 = 16'sh0;
  wire signed [15:0] n133 = 16'sh0;
  wire signed [15:0] n134 = 16'sh0;
  wire signed [15:0] n135 = 16'sh0;
  wire signed [15:0] n136 = 16'sh0;
  always @(posedge clk) begin
    if (rst) begin
      n1 <= 16'sh0;
      n2 <= 16'sh0;
      n3 <= 16'sh0;
      n4 <= 16'sh0;
      n5 <= 16'sh0;
      n6 <= 16'sh0;
      n7 <= 16'sh0;
      n8 <= 16'sh0;
      n9 <= 16'sh0;
      n10 <= 16'sh0;
      n11 <= 16'sh0;
      n12 <= 16'sh0;
      n13 <= 16'sh0;
      n14 <= 16'sh0;
      n15 <= 16'sh0;
    end else begin
      n1 <= n58;
      n2 <= n62;
      n3 <= n66;
      n4 <= n70;
      n5 <= n86;
      n6 <= n92;
      n7 <= n98;
      n8 <= n102;
      n9 <= n108;
      n10 <= n107;
      n11 <= n121;
      n12 <= n122;
      n13 <= n123;
      n14 <= n124;
      n15 <= n125;
    end
  end
  assign out_line = {n43};
  assign out_lg = {n14, n13, n12, n11};
  assign out_ct = {n15};
endmodule