// counter: generated by xetal-fpga from an X_eTaL program; do not edit.
// Clocked: registers from reset, one stream item per clock.
module counter (
  input  wire clk,
  input  wire rst,
  output wire [15:0] out_s
);
  reg signed [15:0] n0;
  wire signed [15:0] n1 = 16'sh1;
  wire signed [15:0] n2 = n0 + n1;
  always @(posedge clk) begin
    if (rst) begin
      n0 <= 16'shfffa;
    end else begin
      n0 <= n2;
    end
  end
  assign out_s = {n0};
endmodule