// vector_add: generated by xetal-fpga from an X_eTaL program; do not edit.
// Spatial schedule: 8 lane(s), combinational.
module vector_add (
  input  wire [127:0] in_a,
  input  wire [127:0] in_b,
  output wire [127:0] out_c
);
  wire signed [15:0] n0 = in_a[15:0];
  wire signed [15:0] n1 = in_a[31:16];
  wire signed [15:0] n2 = in_a[47:32];
  wire signed [15:0] n3 = in_a[63:48];
  wire signed [15:0] n4 = in_a[79:64];
  wire signed [15:0] n5 = in_a[95:80];
  wire signed [15:0] n6 = in_a[111:96];
  wire signed [15:0] n7 = in_a[127:112];
  wire signed [15:0] n8 = in_b[15:0];
  wire signed [15:0] n9 = in_b[31:16];
  wire signed [15:0] n10 = in_b[47:32];
  wire signed [15:0] n11 = in_b[63:48];
  wire signed [15:0] n12 = in_b[79:64];
  wire signed [15:0] n13 = in_b[95:80];
  wire signed [15:0] n14 = in_b[111:96];
  wire signed [15:0] n15 = in_b[127:112];
  wire signed [15:0] n16 = n0 + n8;
  wire signed [15:0] n17 = n1 + n9;
  wire signed [15:0] n18 = n2 + n10;
  wire signed [15:0] n19 = n3 + n11;
  wire signed [15:0] n20 = n4 + n12;
  wire signed [15:0] n21 = n5 + n13;
  wire signed [15:0] n22 = n6 + n14;
  wire signed [15:0] n23 = n7 + n15;
  assign out_c = {n23, n22, n21, n20, n19, n18, n17, n16};
endmodule