// vector_add: generated by xetal-fpga from an X_eTaL program; do not edit.
// Temporal schedule: 1 lane(s), done after 8 clock(s) from reset.
module vector_add (
  input  wire clk,
  input  wire rst,
  input  wire [127:0] in_a,
  input  wire [127:0] in_b,
  output wire [127:0] out_c,
  output wire done
);
  reg signed [4:0] n0;
  reg signed [15:0] n32;
  reg signed [15:0] n36;
  reg signed [15:0] n40;
  reg signed [15:0] n44;
  reg signed [15:0] n48;
  reg signed [15:0] n52;
  reg signed [15:0] n56;
  reg signed [15:0] n60;
  wire signed [4:0] n1 = 5'sh8;
  wire signed [4:0] n2 = 5'sh1;
  wire n3 = n0 < n1;
  wire signed [4:0] n4 = n0 + n2;
  wire signed [4:0] n5 = n3 ? n4 : n0;
  wire n6 = n0 >= n1;
  wire signed [4:0] n7 = 5'sh1;
  wire signed [4:0] n8 = n0 * n7;
  wire signed [4:0] n9 = 5'sh0;
  wire signed [4:0] n10 = n8 + n9;
  wire signed [15:0] n11 = in_a[15:0];
  wire signed [15:0] n12 = in_a[31:16];
  wire signed [15:0] n13 = in_a[47:32];
  wire signed [15:0] n14 = in_a[63:48];
  wire signed [15:0] n15 = in_a[79:64];
  wire signed [15:0] n16 = in_a[95:80];
  wire signed [15:0] n17 = in_a[111:96];
  wire signed [15:0] n18 = in_a[127:112];
  wire signed [15:0] n19 = (n10 == 0) ? n11 : (n10 == 1) ? n12 : (n10 == 2) ? n13 : (n10 == 3) ? n14 : (n10 == 4) ? n15 : (n10 == 5) ? n16 : (n10 == 6) ? n17 : (n10 == 7) ? n18 : 16'sh0;
  wire signed [15:0] n20 = in_b[15:0];
  wire signed [15:0] n21 = in_b[31:16];
  wire signed [15:0] n22 = in_b[47:32];
  wire signed [15:0] n23 = in_b[63:48];
  wire signed [15:0] n24 = in_b[79:64];
  wire signed [15:0] n25 = in_b[95:80];
  wire signed [15:0] n26 = in_b[111:96];
  wire signed [15:0] n27 = in_b[127:112];
  wire signed [15:0] n28 = (n10 == 0) ? n20 : (n10 == 1) ? n21 : (n10 == 2) ? n22 : (n10 == 3) ? n23 : (n10 == 4) ? n24 : (n10 == 5) ? n25 : (n10 == 6) ? n26 : (n10 == 7) ? n27 : 16'sh0;
  wire signed [15:0] n29 = n19 + n28;
  wire signed [4:0] n30 = 5'sh0;
  wire n31 = n0 == n30;
  wire signed [15:0] n33 = n31 ? n29 : n32;
  wire signed [4:0] n34 = 5'sh1;
  wire n35 = n0 == n34;
  wire signed [15:0] n37 = n35 ? n29 : n36;
  wire signed [4:0] n38 = 5'sh2;
  wire n39 = n0 == n38;
  wire signed [15:0] n41 = n39 ? n29 : n40;
  wire signed [4:0] n42 = 5'sh3;
  wire n43 = n0 == n42;
  wire signed [15:0] n45 = n43 ? n29 : n44;
  wire signed [4:0] n46 = 5'sh4;
  wire n47 = n0 == n46;
  wire signed [15:0] n49 = n47 ? n29 : n48;
  wire signed [4:0] n50 = 5'sh5;
  wire n51 = n0 == n50;
  wire signed [15:0] n53 = n51 ? n29 : n52;
  wire signed [4:0] n54 = 5'sh6;
  wire n55 = n0 == n54;
  wire signed [15:0] n57 = n55 ? n29 : n56;
  wire signed [4:0] n58 = 5'sh7;
  wire n59 = n0 == n58;
  wire signed [15:0] n61 = n59 ? n29 : n60;
  always @(posedge clk) begin
    if (rst) begin
      n0 <= 5'sh0;
      n32 <= 16'sh0;
      n36 <= 16'sh0;
      n40 <= 16'sh0;
      n44 <= 16'sh0;
      n48 <= 16'sh0;
      n52 <= 16'sh0;
      n56 <= 16'sh0;
      n60 <= 16'sh0;
    end else begin
      n0 <= n5;
      n32 <= n33;
      n36 <= n37;
      n40 <= n41;
      n44 <= n45;
      n48 <= n49;
      n52 <= n53;
      n56 <= n57;
      n60 <= n61;
    end
  end
  assign out_c = {n60, n56, n52, n48, n44, n40, n36, n32};
  assign done = n6;
endmodule