// threshold: generated by xetal-fpga from an X_eTaL program; do not edit.
// Spatial schedule: 8 lane(s), combinational.
module threshold (
  input  wire [127:0] in_x,
  output wire [7:0] out_m,
  output wire [127:0] out_kept,
  output wire [127:0] out_relu
);
  wire signed [15:0] n0 = in_x[15:0];
  wire signed [15:0] n1 = in_x[31:16];
  wire signed [15:0] n2 = in_x[47:32];
  wire signed [15:0] n3 = in_x[63:48];
  wire signed [15:0] n4 = in_x[79:64];
  wire signed [15:0] n5 = in_x[95:80];
  wire signed [15:0] n6 = in_x[111:96];
  wire signed [15:0] n7 = in_x[127:112];
  wire signed [15:0] n8 = 16'sh4;
  wire signed [15:0] n9 = 16'sh0;
  wire n10 = n0 > n8;
  wire n11 = n1 > n8;
  wire n12 = n2 > n8;
  wire n13 = n3 > n8;
  wire n14 = n4 > n8;
  wire n15 = n5 > n8;
  wire n16 = n6 > n8;
  wire n17 = n7 > n8;
  wire signed [15:0] n18 = n10 ? n0 : n9;
  wire signed [15:0] n19 = n11 ? n1 : n9;
  wire signed [15:0] n20 = n12 ? n2 : n9;
  wire signed [15:0] n21 = n13 ? n3 : n9;
  wire signed [15:0] n22 = n14 ? n4 : n9;
  wire signed [15:0] n23 = n15 ? n5 : n9;
  wire signed [15:0] n24 = n16 ? n6 : n9;
  wire signed [15:0] n25 = n17 ? n7 : n9;
  wire signed [15:0] n26 = (n0 > n9) ? n0 : n9;
  wire signed [15:0] n27 = (n1 > n9) ? n1 : n9;
  wire signed [15:0] n28 = (n2 > n9) ? n2 : n9;
  wire signed [15:0] n29 = (n3 > n9) ? n3 : n9;
  wire signed [15:0] n30 = (n4 > n9) ? n4 : n9;
  wire signed [15:0] n31 = (n5 > n9) ? n5 : n9;
  wire signed [15:0] n32 = (n6 > n9) ? n6 : n9;
  wire signed [15:0] n33 = (n7 > n9) ? n7 : n9;
  assign out_m = {n17, n16, n15, n14, n13, n12, n11, n10};
  assign out_kept = {n25, n24, n23, n22, n21, n20, n19, n18};
  assign out_relu = {n33, n32, n31, n30, n29, n28, n27, n26};
endmodule