// threshold: generated by xetal-fpga from an X_eTaL program; do not edit.
// Temporal schedule: 1 lane(s), done after 8 clock(s) from reset.
module threshold (
  input  wire clk,
  input  wire rst,
  input  wire [127:0] in_x,
  output wire [7:0] out_m,
  output wire [127:0] out_kept,
  output wire [127:0] out_relu,
  output wire done
);
  reg signed [4:0] n0;
  reg n27;
  reg n31;
  reg n35;
  reg n39;
  reg n43;
  reg n47;
  reg n51;
  reg n55;
  reg signed [15:0] n59;
  reg signed [15:0] n63;
  reg signed [15:0] n67;
  reg signed [15:0] n71;
  reg signed [15:0] n75;
  reg signed [15:0] n79;
  reg signed [15:0] n83;
  reg signed [15:0] n87;
  reg signed [15:0] n91;
  reg signed [15:0] n95;
  reg signed [15:0] n99;
  reg signed [15:0] n103;
  reg signed [15:0] n107;
  reg signed [15:0] n111;
  reg signed [15:0] n115;
  reg signed [15:0] n119;
  reg signed [15:0] n123;
  reg signed [15:0] n127;
  reg signed [15:0] n131;
  reg signed [15:0] n135;
  reg signed [15:0] n139;
  reg signed [15:0] n143;
  reg signed [15:0] n147;
  reg signed [15:0] n151;
  wire signed [4:0] n1 = 5'sh8;
  wire signed [4:0] n2 = 5'sh1;
  wire n3 = n0 < n1;
  wire signed [4:0] n4 = n0 + n2;
  wire signed [4:0] n5 = n3 ? n4 : n0;
  wire n6 = n0 >= n1;
  wire signed [4:0] n7 = 5'sh1;
  wire signed [4:0] n8 = n0 * n7;
  wire signed [4:0] n9 = 5'sh0;
  wire signed [4:0] n10 = n8 + n9;
  wire signed [15:0] n11 = in_x[15:0];
  wire signed [15:0] n12 = in_x[31:16];
  wire signed [15:0] n13 = in_x[47:32];
  wire signed [15:0] n14 = in_x[63:48];
  wire signed [15:0] n15 = in_x[79:64];
  wire signed [15:0] n16 = in_x[95:80];
  wire signed [15:0] n17 = in_x[111:96];
  wire signed [15:0] n18 = in_x[127:112];
  wire signed [15:0] n19 = (n10 == 0) ? n11 : (n10 == 1) ? n12 : (n10 == 2) ? n13 : (n10 == 3) ? n14 : (n10 == 4) ? n15 : (n10 == 5) ? n16 : (n10 == 6) ? n17 : (n10 == 7) ? n18 : 16'sh0;
  wire signed [15:0] n20 = 16'sh4;
  wire signed [15:0] n21 = 16'sh0;
  wire n22 = n19 > n20;
  wire signed [15:0] n23 = n22 ? n19 : n21;
  wire signed [15:0] n24 = (n19 > n21) ? n19 : n21;
  wire signed [4:0] n25 = 5'sh0;
  wire n26 = n0 == n25;
  wire n28 = n26 ? n22 : n27;
  wire signed [4:0] n29 = 5'sh1;
  wire n30 = n0 == n29;
  wire n32 = n30 ? n22 : n31;
  wire signed [4:0] n33 = 5'sh2;
  wire n34 = n0 == n33;
  wire n36 = n34 ? n22 : n35;
  wire signed [4:0] n37 = 5'sh3;
  wire n38 = n0 == n37;
  wire n40 = n38 ? n22 : n39;
  wire signed [4:0] n41 = 5'sh4;
  wire n42 = n0 == n41;
  wire n44 = n42 ? n22 : n43;
  wire signed [4:0] n45 = 5'sh5;
  wire n46 = n0 == n45;
  wire n48 = n46 ? n22 : n47;
  wire signed [4:0] n49 = 5'sh6;
  wire n50 = n0 == n49;
  wire n52 = n50 ? n22 : n51;
  wire signed [4:0] n53 = 5'sh7;
  wire n54 = n0 == n53;
  wire n56 = n54 ? n22 : n55;
  wire signed [4:0] n57 = 5'sh0;
  wire n58 = n0 == n57;
  wire signed [15:0] n60 = n58 ? n23 : n59;
  wire signed [4:0] n61 = 5'sh1;
  wire n62 = n0 == n61;
  wire signed [15:0] n64 = n62 ? n23 : n63;
  wire signed [4:0] n65 = 5'sh2;
  wire n66 = n0 == n65;
  wire signed [15:0] n68 = n66 ? n23 : n67;
  wire signed [4:0] n69 = 5'sh3;
  wire n70 = n0 == n69;
  wire signed [15:0] n72 = n70 ? n23 : n71;
  wire signed [4:0] n73 = 5'sh4;
  wire n74 = n0 == n73;
  wire signed [15:0] n76 = n74 ? n23 : n75;
  wire signed [4:0] n77 = 5'sh5;
  wire n78 = n0 == n77;
  wire signed [15:0] n80 = n78 ? n23 : n79;
  wire signed [4:0] n81 = 5'sh6;
  wire n82 = n0 == n81;
  wire signed [15:0] n84 = n82 ? n23 : n83;
  wire signed [4:0] n85 = 5'sh7;
  wire n86 = n0 == n85;
  wire signed [15:0] n88 = n86 ? n23 : n87;
  wire signed [4:0] n89 = 5'sh0;
  wire n90 = n0 == n89;
  wire signed [15:0] n92 = n90 ? n23 : n91;
  wire signed [4:0] n93 = 5'sh1;
  wire n94 = n0 == n93;
  wire signed [15:0] n96 = n94 ? n23 : n95;
  wire signed [4:0] n97 = 5'sh2;
  wire n98 = n0 == n97;
  wire signed [15:0] n100 = n98 ? n23 : n99;
  wire signed [4:0] n101 = 5'sh3;
  wire n102 = n0 == n101;
  wire signed [15:0] n104 = n102 ? n23 : n103;
  wire signed [4:0] n105 = 5'sh4;
  wire n106 = n0 == n105;
  wire signed [15:0] n108 = n106 ? n23 : n107;
  wire signed [4:0] n109 = 5'sh5;
  wire n110 = n0 == n109;
  wire signed [15:0] n112 = n110 ? n23 : n111;
  wire signed [4:0] n113 = 5'sh6;
  wire n114 = n0 == n113;
  wire signed [15:0] n116 = n114 ? n23 : n115;
  wire signed [4:0] n117 = 5'sh7;
  wire n118 = n0 == n117;
  wire signed [15:0] n120 = n118 ? n23 : n119;
  wire signed [4:0] n121 = 5'sh0;
  wire n122 = n0 == n121;
  wire signed [15:0] n124 = n122 ? n24 : n123;
  wire signed [4:0] n125 = 5'sh1;
  wire n126 = n0 == n125;
  wire signed [15:0] n128 = n126 ? n24 : n127;
  wire signed [4:0] n129 = 5'sh2;
  wire n130 = n0 == n129;
  wire signed [15:0] n132 = n130 ? n24 : n131;
  wire signed [4:0] n133 = 5'sh3;
  wire n134 = n0 == n133;
  wire signed [15:0] n136 = n134 ? n24 : n135;
  wire signed [4:0] n137 = 5'sh4;
  wire n138 = n0 == n137;
  wire signed [15:0] n140 = n138 ? n24 : n139;
  wire signed [4:0] n141 = 5'sh5;
  wire n142 = n0 == n141;
  wire signed [15:0] n144 = n142 ? n24 : n143;
  wire signed [4:0] n145 = 5'sh6;
  wire n146 = n0 == n145;
  wire signed [15:0] n148 = n146 ? n24 : n147;
  wire signed [4:0] n149 = 5'sh7;
  wire n150 = n0 == n149;
  wire signed [15:0] n152 = n150 ? n24 : n151;
  always @(posedge clk) begin
    if (rst) begin
      n0 <= 5'sh0;
      n27 <= 1'b0;
      n31 <= 1'b0;
      n35 <= 1'b0;
      n39 <= 1'b0;
      n43 <= 1'b0;
      n47 <= 1'b0;
      n51 <= 1'b0;
      n55 <= 1'b0;
      n59 <= 16'sh0;
      n63 <= 16'sh0;
      n67 <= 16'sh0;
      n71 <= 16'sh0;
      n75 <= 16'sh0;
      n79 <= 16'sh0;
      n83 <= 16'sh0;
      n87 <= 16'sh0;
      n91 <= 16'sh0;
      n95 <= 16'sh0;
      n99 <= 16'sh0;
      n103 <= 16'sh0;
      n107 <= 16'sh0;
      n111 <= 16'sh0;
      n115 <= 16'sh0;
      n119 <= 16'sh0;
      n123 <= 16'sh0;
      n127 <= 16'sh0;
      n131 <= 16'sh0;
      n135 <= 16'sh0;
      n139 <= 16'sh0;
      n143 <= 16'sh0;
      n147 <= 16'sh0;
      n151 <= 16'sh0;
    end else begin
      n0 <= n5;
      n27 <= n28;
      n31 <= n32;
      n35 <= n36;
      n39 <= n40;
      n43 <= n44;
      n47 <= n48;
      n51 <= n52;
      n55 <= n56;
      n59 <= n60;
      n63 <= n64;
      n67 <= n68;
      n71 <= n72;
      n75 <= n76;
      n79 <= n80;
      n83 <= n84;
      n87 <= n88;
      n91 <= n92;
      n95 <= n96;
      n99 <= n100;
      n103 <= n104;
      n107 <= n108;
      n111 <= n112;
      n115 <= n116;
      n119 <= n120;
      n123 <= n124;
      n127 <= n128;
      n131 <= n132;
      n135 <= n136;
      n139 <= n140;
      n143 <= n144;
      n147 <= n148;
      n151 <= n152;
    end
  end
  assign out_m = {n55, n51, n47, n43, n39, n35, n31, n27};
  assign out_kept = {n87, n83, n79, n75, n71, n67, n63, n59};
  assign out_relu = {n151, n147, n143, n139, n135, n131, n127, n123};
  assign done = n6;
endmodule