// saxpy: generated by xetal-fpga from an X_eTaL program; do not edit.
// Spatial schedule: 8 lane(s), combinational.
module saxpy (
  input  wire [127:0] in_x,
  input  wire [127:0] in_y,
  output wire [127:0] out_r,
  output wire [127:0] out_rb
);
  wire signed [15:0] n0 = in_x[15:0];
  wire signed [15:0] n1 = in_x[31:16];
  wire signed [15:0] n2 = in_x[47:32];
  wire signed [15:0] n3 = in_x[63:48];
  wire signed [15:0] n4 = in_x[79:64];
  wire signed [15:0] n5 = in_x[95:80];
  wire signed [15:0] n6 = in_x[111:96];
  wire signed [15:0] n7 = in_x[127:112];
  wire signed [15:0] n8 = in_y[15:0];
  wire signed [15:0] n9 = in_y[31:16];
  wire signed [15:0] n10 = in_y[47:32];
  wire signed [15:0] n11 = in_y[63:48];
  wire signed [15:0] n12 = in_y[79:64];
  wire signed [15:0] n13 = in_y[95:80];
  wire signed [15:0] n14 = in_y[111:96];
  wire signed [15:0] n15 = in_y[127:112];
  wire signed [15:0] n16 = 16'sh3;
  wire signed [15:0] n17 = n16 * n0;
  wire signed [15:0] n18 = n16 * n1;
  wire signed [15:0] n19 = n16 * n2;
  wire signed [15:0] n20 = n16 * n3;
  wire signed [15:0] n21 = n16 * n4;
  wire signed [15:0] n22 = n16 * n5;
  wire signed [15:0] n23 = n16 * n6;
  wire signed [15:0] n24 = n16 * n7;
  wire signed [15:0] n25 = n8 + n17;
  wire signed [15:0] n26 = n9 + n18;
  wire signed [15:0] n27 = n10 + n19;
  wire signed [15:0] n28 = n11 + n20;
  wire signed [15:0] n29 = n12 + n21;
  wire signed [15:0] n30 = n13 + n22;
  wire signed [15:0] n31 = n14 + n23;
  wire signed [15:0] n32 = n15 + n24;
  wire signed [15:0] n33 = 16'sh2710;
  wire signed [15:0] n34 = n33 * n0;
  wire signed [15:0] n35 = n33 * n1;
  wire signed [15:0] n36 = n33 * n2;
  wire signed [15:0] n37 = n33 * n3;
  wire signed [15:0] n38 = n33 * n4;
  wire signed [15:0] n39 = n33 * n5;
  wire signed [15:0] n40 = n33 * n6;
  wire signed [15:0] n41 = n33 * n7;
  wire signed [15:0] n42 = n8 + n34;
  wire signed [15:0] n43 = n9 + n35;
  wire signed [15:0] n44 = n10 + n36;
  wire signed [15:0] n45 = n11 + n37;
  wire signed [15:0] n46 = n12 + n38;
  wire signed [15:0] n47 = n13 + n39;
  wire signed [15:0] n48 = n14 + n40;
  wire signed [15:0] n49 = n15 + n41;
  assign out_r = {n32, n31, n30, n29, n28, n27, n26, n25};
  assign out_rb = {n49, n48, n47, n46, n45, n44, n43, n42};
endmodule