// saxpy: generated by xetal-fpga from an X_eTaL program; do not edit.
// Temporal schedule: 1 lane(s), done after 8 clock(s) from reset.
module saxpy (
  input  wire clk,
  input  wire rst,
  input  wire [127:0] in_x,
  input  wire [127:0] in_y,
  output wire [127:0] out_r,
  output wire [127:0] out_rb,
  output wire done
);
  reg signed [4:0] n0;
  reg signed [15:0] n37;
  reg signed [15:0] n41;
  reg signed [15:0] n45;
  reg signed [15:0] n49;
  reg signed [15:0] n53;
  reg signed [15:0] n57;
  reg signed [15:0] n61;
  reg signed [15:0] n65;
  reg signed [15:0] n69;
  reg signed [15:0] n73;
  reg signed [15:0] n77;
  reg signed [15:0] n81;
  reg signed [15:0] n85;
  reg signed [15:0] n89;
  reg signed [15:0] n93;
  reg signed [15:0] n97;
  wire signed [4:0] n1 = 5'sh8;
  wire signed [4:0] n2 = 5'sh1;
  wire n3 = n0 < n1;
  wire signed [4:0] n4 = n0 + n2;
  wire signed [4:0] n5 = n3 ? n4 : n0;
  wire n6 = n0 >= n1;
  wire signed [4:0] n7 = 5'sh1;
  wire signed [4:0] n8 = n0 * n7;
  wire signed [4:0] n9 = 5'sh0;
  wire signed [4:0] n10 = n8 + n9;
  wire signed [15:0] n11 = in_x[15:0];
  wire signed [15:0] n12 = in_x[31:16];
  wire signed [15:0] n13 = in_x[47:32];
  wire signed [15:0] n14 = in_x[63:48];
  wire signed [15:0] n15 = in_x[79:64];
  wire signed [15:0] n16 = in_x[95:80];
  wire signed [15:0] n17 = in_x[111:96];
  wire signed [15:0] n18 = in_x[127:112];
  wire signed [15:0] n19 = (n10 == 0) ? n11 : (n10 == 1) ? n12 : (n10 == 2) ? n13 : (n10 == 3) ? n14 : (n10 == 4) ? n15 : (n10 == 5) ? n16 : (n10 == 6) ? n17 : (n10 == 7) ? n18 : 16'sh0;
  wire signed [15:0] n20 = in_y[15:0];
  wire signed [15:0] n21 = in_y[31:16];
  wire signed [15:0] n22 = in_y[47:32];
  wire signed [15:0] n23 = in_y[63:48];
  wire signed [15:0] n24 = in_y[79:64];
  wire signed [15:0] n25 = in_y[95:80];
  wire signed [15:0] n26 = in_y[111:96];
  wire signed [15:0] n27 = in_y[127:112];
  wire signed [15:0] n28 = (n10 == 0) ? n20 : (n10 == 1) ? n21 : (n10 == 2) ? n22 : (n10 == 3) ? n23 : (n10 == 4) ? n24 : (n10 == 5) ? n25 : (n10 == 6) ? n26 : (n10 == 7) ? n27 : 16'sh0;
  wire signed [15:0] n29 = 16'sh3;
  wire signed [15:0] n30 = n29 * n19;
  wire signed [15:0] n31 = n28 + n30;
  wire signed [15:0] n32 = 16'sh2710;
  wire signed [15:0] n33 = n32 * n19;
  wire signed [15:0] n34 = n28 + n33;
  wire signed [4:0] n35 = 5'sh0;
  wire n36 = n0 == n35;
  wire signed [15:0] n38 = n36 ? n31 : n37;
  wire signed [4:0] n39 = 5'sh1;
  wire n40 = n0 == n39;
  wire signed [15:0] n42 = n40 ? n31 : n41;
  wire signed [4:0] n43 = 5'sh2;
  wire n44 = n0 == n43;
  wire signed [15:0] n46 = n44 ? n31 : n45;
  wire signed [4:0] n47 = 5'sh3;
  wire n48 = n0 == n47;
  wire signed [15:0] n50 = n48 ? n31 : n49;
  wire signed [4:0] n51 = 5'sh4;
  wire n52 = n0 == n51;
  wire signed [15:0] n54 = n52 ? n31 : n53;
  wire signed [4:0] n55 = 5'sh5;
  wire n56 = n0 == n55;
  wire signed [15:0] n58 = n56 ? n31 : n57;
  wire signed [4:0] n59 = 5'sh6;
  wire n60 = n0 == n59;
  wire signed [15:0] n62 = n60 ? n31 : n61;
  wire signed [4:0] n63 = 5'sh7;
  wire n64 = n0 == n63;
  wire signed [15:0] n66 = n64 ? n31 : n65;
  wire signed [4:0] n67 = 5'sh0;
  wire n68 = n0 == n67;
  wire signed [15:0] n70 = n68 ? n34 : n69;
  wire signed [4:0] n71 = 5'sh1;
  wire n72 = n0 == n71;
  wire signed [15:0] n74 = n72 ? n34 : n73;
  wire signed [4:0] n75 = 5'sh2;
  wire n76 = n0 == n75;
  wire signed [15:0] n78 = n76 ? n34 : n77;
  wire signed [4:0] n79 = 5'sh3;
  wire n80 = n0 == n79;
  wire signed [15:0] n82 = n80 ? n34 : n81;
  wire signed [4:0] n83 = 5'sh4;
  wire n84 = n0 == n83;
  wire signed [15:0] n86 = n84 ? n34 : n85;
  wire signed [4:0] n87 = 5'sh5;
  wire n88 = n0 == n87;
  wire signed [15:0] n90 = n88 ? n34 : n89;
  wire signed [4:0] n91 = 5'sh6;
  wire n92 = n0 == n91;
  wire signed [15:0] n94 = n92 ? n34 : n93;
  wire signed [4:0] n95 = 5'sh7;
  wire n96 = n0 == n95;
  wire signed [15:0] n98 = n96 ? n34 : n97;
  always @(posedge clk) begin
    if (rst) begin
      n0 <= 5'sh0;
      n37 <= 16'sh0;
      n41 <= 16'sh0;
      n45 <= 16'sh0;
      n49 <= 16'sh0;
      n53 <= 16'sh0;
      n57 <= 16'sh0;
      n61 <= 16'sh0;
      n65 <= 16'sh0;
      n69 <= 16'sh0;
      n73 <= 16'sh0;
      n77 <= 16'sh0;
      n81 <= 16'sh0;
      n85 <= 16'sh0;
      n89 <= 16'sh0;
      n93 <= 16'sh0;
      n97 <= 16'sh0;
    end else begin
      n0 <= n5;
      n37 <= n38;
      n41 <= n42;
      n45 <= n46;
      n49 <= n50;
      n53 <= n54;
      n57 <= n58;
      n61 <= n62;
      n65 <= n66;
      n69 <= n70;
      n73 <= n74;
      n77 <= n78;
      n81 <= n82;
      n85 <= n86;
      n89 <= n90;
      n93 <= n94;
      n97 <= n98;
    end
  end
  assign out_r = {n65, n61, n57, n53, n49, n45, n41, n37};
  assign out_rb = {n97, n93, n89, n85, n81, n77, n73, n69};
  assign done = n6;
endmodule