// reduce_sum: generated by xetal-fpga from an X_eTaL program; do not edit.
// Spatial schedule: 8 lane(s), combinational.
module reduce_sum (
  input  wire [127:0] in_v,
  input  wire [127:0] in_big,
  output wire [15:0] out_s,
  output wire [15:0] out_sb,
  output wire [15:0] out_l
);
  wire signed [15:0] n0 = in_v[15:0];
  wire signed [15:0] n1 = in_v[31:16];
  wire signed [15:0] n2 = in_v[47:32];
  wire signed [15:0] n3 = in_v[63:48];
  wire signed [15:0] n4 = in_v[79:64];
  wire signed [15:0] n5 = in_v[95:80];
  wire signed [15:0] n6 = in_v[111:96];
  wire signed [15:0] n7 = in_v[127:112];
  wire signed [15:0] n8 = in_big[15:0];
  wire signed [15:0] n9 = in_big[31:16];
  wire signed [15:0] n10 = in_big[47:32];
  wire signed [15:0] n11 = in_big[63:48];
  wire signed [15:0] n12 = in_big[79:64];
  wire signed [15:0] n13 = in_big[95:80];
  wire signed [15:0] n14 = in_big[111:96];
  wire signed [15:0] n15 = in_big[127:112];
  wire signed [15:0] n16 = n0 + n4;
  wire signed [15:0] n17 = n1 + n5;
  wire signed [15:0] n18 = n2 + n6;
  wire signed [15:0] n19 = n3 + n7;
  wire signed [15:0] n20 = n16 + n18;
  wire signed [15:0] n21 = n17 + n19;
  wire signed [15:0] n22 = n20 + n21;
  wire signed [15:0] n23 = n8 + n12;
  wire signed [15:0] n24 = n9 + n13;
  wire signed [15:0] n25 = n10 + n14;
  wire signed [15:0] n26 = n11 + n15;
  wire signed [15:0] n27 = n23 + n25;
  wire signed [15:0] n28 = n24 + n26;
  wire signed [15:0] n29 = n27 + n28;
  wire signed [15:0] n30 = (n0 > n4) ? n0 : n4;
  wire signed [15:0] n31 = (n1 > n5) ? n1 : n5;
  wire signed [15:0] n32 = (n2 > n6) ? n2 : n6;
  wire signed [15:0] n33 = (n3 > n7) ? n3 : n7;
  wire signed [15:0] n34 = (n30 > n32) ? n30 : n32;
  wire signed [15:0] n35 = (n31 > n33) ? n31 : n33;
  wire signed [15:0] n36 = (n34 > n35) ? n34 : n35;
  assign out_s = {n22};
  assign out_sb = {n29};
  assign out_l = {n36};
endmodule