// reduce_sum: generated by xetal-fpga from an X_eTaL program; do not edit.
// Temporal schedule: 1 lane(s), done after 8 clock(s) from reset.
module reduce_sum (
  input  wire clk,
  input  wire rst,
  input  wire [127:0] in_v,
  input  wire [127:0] in_big,
  output wire [15:0] out_s,
  output wire [15:0] out_sb,
  output wire [15:0] out_l,
  output wire done
);
  reg signed [4:0] n0;
  reg signed [15:0] n30;
  reg signed [15:0] n34;
  reg signed [15:0] n38;
  wire signed [4:0] n1 = 5'sh8;
  wire signed [4:0] n2 = 5'sh1;
  wire n3 = n0 < n1;
  wire signed [4:0] n4 = n0 + n2;
  wire signed [4:0] n5 = n3 ? n4 : n0;
  wire n6 = n0 >= n1;
  wire signed [4:0] n7 = 5'sh1;
  wire signed [4:0] n8 = n0 * n7;
  wire signed [4:0] n9 = 5'sh0;
  wire signed [4:0] n10 = n8 + n9;
  wire signed [15:0] n11 = in_v[15:0];
  wire signed [15:0] n12 = in_v[31:16];
  wire signed [15:0] n13 = in_v[47:32];
  wire signed [15:0] n14 = in_v[63:48];
  wire signed [15:0] n15 = in_v[79:64];
  wire signed [15:0] n16 = in_v[95:80];
  wire signed [15:0] n17 = in_v[111:96];
  wire signed [15:0] n18 = in_v[127:112];
  wire signed [15:0] n19 = (n10 == 0) ? n11 : (n10 == 1) ? n12 : (n10 == 2) ? n13 : (n10 == 3) ? n14 : (n10 == 4) ? n15 : (n10 == 5) ? n16 : (n10 == 6) ? n17 : (n10 == 7) ? n18 : 16'sh0;
  wire signed [15:0] n20 = in_big[15:0];
  wire signed [15:0] n21 = in_big[31:16];
  wire signed [15:0] n22 = in_big[47:32];
  wire signed [15:0] n23 = in_big[63:48];
  wire signed [15:0] n24 = in_big[79:64];
  wire signed [15:0] n25 = in_big[95:80];
  wire signed [15:0] n26 = in_big[111:96];
  wire signed [15:0] n27 = in_big[127:112];
  wire signed [15:0] n28 = (n10 == 0) ? n20 : (n10 == 1) ? n21 : (n10 == 2) ? n22 : (n10 == 3) ? n23 : (n10 == 4) ? n24 : (n10 == 5) ? n25 : (n10 == 6) ? n26 : (n10 == 7) ? n27 : 16'sh0;
  wire signed [15:0] n29 = 16'sh0;
  wire signed [15:0] n31 = n30 + n19;
  wire signed [15:0] n32 = n3 ? n31 : n30;
  wire signed [15:0] n33 = 16'sh0;
  wire signed [15:0] n35 = n34 + n28;
  wire signed [15:0] n36 = n3 ? n35 : n34;
  wire signed [15:0] n37 = 16'sh8000;
  wire signed [15:0] n39 = (n38 > n19) ? n38 : n19;
  wire signed [15:0] n40 = n3 ? n39 : n38;
  always @(posedge clk) begin
    if (rst) begin
      n0 <= 5'sh0;
      n30 <= 16'sh0;
      n34 <= 16'sh0;
      n38 <= 16'sh8000;
    end else begin
      n0 <= n5;
      n30 <= n32;
      n34 <= n36;
      n38 <= n40;
    end
  end
  assign out_s = {n30};
  assign out_sb = {n34};
  assign out_l = {n38};
  assign done = n6;
endmodule