// pipeline: generated by xetal-fpga from an X_eTaL program; do not edit.
// Spatial schedule: 8 lane(s), combinational.
module pipeline (
  input  wire [127:0] in_x,
  input  wire [127:0] in_k,
  output wire [127:0] out_s,
  output wire [127:0] out_r,
  output wire [15:0] out_sum
);
  wire signed [15:0] n0 = in_x[15:0];
  wire signed [15:0] n1 = in_x[31:16];
  wire signed [15:0] n2 = in_x[47:32];
  wire signed [15:0] n3 = in_x[63:48];
  wire signed [15:0] n4 = in_x[79:64];
  wire signed [15:0] n5 = in_x[95:80];
  wire signed [15:0] n6 = in_x[111:96];
  wire signed [15:0] n7 = in_x[127:112];
  wire signed [15:0] n8 = in_k[15:0];
  wire signed [15:0] n9 = in_k[31:16];
  wire signed [15:0] n10 = in_k[47:32];
  wire signed [15:0] n11 = in_k[63:48];
  wire signed [15:0] n12 = in_k[79:64];
  wire signed [15:0] n13 = in_k[95:80];
  wire signed [15:0] n14 = in_k[111:96];
  wire signed [15:0] n15 = in_k[127:112];
  wire signed [15:0] n16 = 16'sh0;
  wire signed [15:0] n17 = n0 * n8;
  wire signed [15:0] n18 = n1 * n9;
  wire signed [15:0] n19 = n2 * n10;
  wire signed [15:0] n20 = n3 * n11;
  wire signed [15:0] n21 = n4 * n12;
  wire signed [15:0] n22 = n5 * n13;
  wire signed [15:0] n23 = n6 * n14;
  wire signed [15:0] n24 = n7 * n15;
  wire signed [15:0] n25 = n0 + n17;
  wire signed [15:0] n26 = n1 + n18;
  wire signed [15:0] n27 = n2 + n19;
  wire signed [15:0] n28 = n3 + n20;
  wire signed [15:0] n29 = n4 + n21;
  wire signed [15:0] n30 = n5 + n22;
  wire signed [15:0] n31 = n6 + n23;
  wire signed [15:0] n32 = n7 + n24;
  wire signed [15:0] n33 = (n25 > n16) ? n25 : n16;
  wire signed [15:0] n34 = (n26 > n16) ? n26 : n16;
  wire signed [15:0] n35 = (n27 > n16) ? n27 : n16;
  wire signed [15:0] n36 = (n28 > n16) ? n28 : n16;
  wire signed [15:0] n37 = (n29 > n16) ? n29 : n16;
  wire signed [15:0] n38 = (n30 > n16) ? n30 : n16;
  wire signed [15:0] n39 = (n31 > n16) ? n31 : n16;
  wire signed [15:0] n40 = (n32 > n16) ? n32 : n16;
  wire signed [15:0] n41 = n33 + n37;
  wire signed [15:0] n42 = n34 + n38;
  wire signed [15:0] n43 = n35 + n39;
  wire signed [15:0] n44 = n36 + n40;
  wire signed [15:0] n45 = n41 + n43;
  wire signed [15:0] n46 = n42 + n44;
  wire signed [15:0] n47 = n45 + n46;
  assign out_s = {n32, n31, n30, n29, n28, n27, n26, n25};
  assign out_r = {n40, n39, n38, n37, n36, n35, n34, n33};
  assign out_sum = {n47};
endmodule