// pipeline: generated by xetal-fpga from an X_eTaL program; do not edit.
// Temporal schedule: 1 lane(s), done after 8 clock(s) from reset.
module pipeline (
  input  wire clk,
  input  wire rst,
  input  wire [127:0] in_x,
  input  wire [127:0] in_k,
  output wire [127:0] out_s,
  output wire [127:0] out_r,
  output wire [15:0] out_sum,
  output wire done
);
  reg signed [4:0] n0;
  reg signed [15:0] n34;
  reg signed [15:0] n39;
  reg signed [15:0] n43;
  reg signed [15:0] n47;
  reg signed [15:0] n51;
  reg signed [15:0] n55;
  reg signed [15:0] n59;
  reg signed [15:0] n63;
  reg signed [15:0] n67;
  reg signed [15:0] n71;
  reg signed [15:0] n75;
  reg signed [15:0] n79;
  reg signed [15:0] n83;
  reg signed [15:0] n87;
  reg signed [15:0] n91;
  reg signed [15:0] n95;
  reg signed [15:0] n99;
  wire signed [4:0] n1 = 5'sh8;
  wire signed [4:0] n2 = 5'sh1;
  wire n3 = n0 < n1;
  wire signed [4:0] n4 = n0 + n2;
  wire signed [4:0] n5 = n3 ? n4 : n0;
  wire n6 = n0 >= n1;
  wire signed [4:0] n7 = 5'sh1;
  wire signed [4:0] n8 = n0 * n7;
  wire signed [4:0] n9 = 5'sh0;
  wire signed [4:0] n10 = n8 + n9;
  wire signed [15:0] n11 = in_x[15:0];
  wire signed [15:0] n12 = in_x[31:16];
  wire signed [15:0] n13 = in_x[47:32];
  wire signed [15:0] n14 = in_x[63:48];
  wire signed [15:0] n15 = in_x[79:64];
  wire signed [15:0] n16 = in_x[95:80];
  wire signed [15:0] n17 = in_x[111:96];
  wire signed [15:0] n18 = in_x[127:112];
  wire signed [15:0] n19 = (n10 == 0) ? n11 : (n10 == 1) ? n12 : (n10 == 2) ? n13 : (n10 == 3) ? n14 : (n10 == 4) ? n15 : (n10 == 5) ? n16 : (n10 == 6) ? n17 : (n10 == 7) ? n18 : 16'sh0;
  wire signed [15:0] n20 = in_k[15:0];
  wire signed [15:0] n21 = in_k[31:16];
  wire signed [15:0] n22 = in_k[47:32];
  wire signed [15:0] n23 = in_k[63:48];
  wire signed [15:0] n24 = in_k[79:64];
  wire signed [15:0] n25 = in_k[95:80];
  wire signed [15:0] n26 = in_k[111:96];
  wire signed [15:0] n27 = in_k[127:112];
  wire signed [15:0] n28 = (n10 == 0) ? n20 : (n10 == 1) ? n21 : (n10 == 2) ? n22 : (n10 == 3) ? n23 : (n10 == 4) ? n24 : (n10 == 5) ? n25 : (n10 == 6) ? n26 : (n10 == 7) ? n27 : 16'sh0;
  wire signed [15:0] n29 = 16'sh0;
  wire signed [15:0] n30 = n19 * n28;
  wire signed [15:0] n31 = n19 + n30;
  wire signed [15:0] n32 = (n31 > n29) ? n31 : n29;
  wire signed [15:0] n33 = 16'sh0;
  wire signed [15:0] n35 = n34 + n32;
  wire signed [15:0] n36 = n3 ? n35 : n34;
  wire signed [4:0] n37 = 5'sh0;
  wire n38 = n0 == n37;
  wire signed [15:0] n40 = n38 ? n31 : n39;
  wire signed [4:0] n41 = 5'sh1;
  wire n42 = n0 == n41;
  wire signed [15:0] n44 = n42 ? n31 : n43;
  wire signed [4:0] n45 = 5'sh2;
  wire n46 = n0 == n45;
  wire signed [15:0] n48 = n46 ? n31 : n47;
  wire signed [4:0] n49 = 5'sh3;
  wire n50 = n0 == n49;
  wire signed [15:0] n52 = n50 ? n31 : n51;
  wire signed [4:0] n53 = 5'sh4;
  wire n54 = n0 == n53;
  wire signed [15:0] n56 = n54 ? n31 : n55;
  wire signed [4:0] n57 = 5'sh5;
  wire n58 = n0 == n57;
  wire signed [15:0] n60 = n58 ? n31 : n59;
  wire signed [4:0] n61 = 5'sh6;
  wire n62 = n0 == n61;
  wire signed [15:0] n64 = n62 ? n31 : n63;
  wire signed [4:0] n65 = 5'sh7;
  wire n66 = n0 == n65;
  wire signed [15:0] n68 = n66 ? n31 : n67;
  wire signed [4:0] n69 = 5'sh0;
  wire n70 = n0 == n69;
  wire signed [15:0] n72 = n70 ? n32 : n71;
  wire signed [4:0] n73 = 5'sh1;
  wire n74 = n0 == n73;
  wire signed [15:0] n76 = n74 ? n32 : n75;
  wire signed [4:0] n77 = 5'sh2;
  wire n78 = n0 == n77;
  wire signed [15:0] n80 = n78 ? n32 : n79;
  wire signed [4:0] n81 = 5'sh3;
  wire n82 = n0 == n81;
  wire signed [15:0] n84 = n82 ? n32 : n83;
  wire signed [4:0] n85 = 5'sh4;
  wire n86 = n0 == n85;
  wire signed [15:0] n88 = n86 ? n32 : n87;
  wire signed [4:0] n89 = 5'sh5;
  wire n90 = n0 == n89;
  wire signed [15:0] n92 = n90 ? n32 : n91;
  wire signed [4:0] n93 = 5'sh6;
  wire n94 = n0 == n93;
  wire signed [15:0] n96 = n94 ? n32 : n95;
  wire signed [4:0] n97 = 5'sh7;
  wire n98 = n0 == n97;
  wire signed [15:0] n100 = n98 ? n32 : n99;
  always @(posedge clk) begin
    if (rst) begin
      n0 <= 5'sh0;
      n34 <= 16'sh0;
      n39 <= 16'sh0;
      n43 <= 16'sh0;
      n47 <= 16'sh0;
      n51 <= 16'sh0;
      n55 <= 16'sh0;
      n59 <= 16'sh0;
      n63 <= 16'sh0;
      n67 <= 16'sh0;
      n71 <= 16'sh0;
      n75 <= 16'sh0;
      n79 <= 16'sh0;
      n83 <= 16'sh0;
      n87 <= 16'sh0;
      n91 <= 16'sh0;
      n95 <= 16'sh0;
      n99 <= 16'sh0;
    end else begin
      n0 <= n5;
      n34 <= n36;
      n39 <= n40;
      n43 <= n44;
      n47 <= n48;
      n51 <= n52;
      n55 <= n56;
      n59 <= n60;
      n63 <= n64;
      n67 <= n68;
      n71 <= n72;
      n75 <= n76;
      n79 <= n80;
      n83 <= n84;
      n87 <= n88;
      n91 <= n92;
      n95 <= n96;
      n99 <= n100;
    end
  end
  assign out_s = {n67, n63, n59, n55, n51, n47, n43, n39};
  assign out_r = {n99, n95, n91, n87, n83, n79, n75, n71};
  assign out_sum = {n34};
  assign done = n6;
endmodule