// shift: generated by xetal-fpga from an X_eTaL program; do not edit.
// Clocked: registers from reset, one stream item per clock.
module shift (
  input  wire clk,
  input  wire rst,
  input  wire [7:0] in_b,
  output wire [31:0] out_s
);
  reg signed [7:0] n1;
  reg signed [7:0] n2;
  reg signed [7:0] n3;
  reg signed [7:0] n4;
  wire signed [7:0] n0 = in_b[7:0];
  always @(posedge clk) begin
    if (rst) begin
      n1 <= 8'sh0;
      n2 <= 8'sh0;
      n3 <= 8'sh0;
      n4 <= 8'sh0;
    end else begin
      n1 <= n2;
      n2 <= n3;
      n3 <= n4;
      n4 <= n0;
    end
  end
  assign out_s = {n4, n3, n2, n1};
endmodule