// ram: generated by xetal-fpga from an X_eTaL program; do not edit.
// Clocked: registers from reset, one stream item per clock.
module ram (
  input  wire clk,
  input  wire rst,
  input  wire [47:0] in_c,
  output wire [63:0] out_mem
);
  reg signed [7:0] n3;
  reg signed [7:0] n4;
  reg signed [7:0] n5;
  reg signed [7:0] n6;
  reg signed [7:0] n7;
  reg signed [7:0] n8;
  reg signed [7:0] n9;
  reg signed [7:0] n10;
  wire signed [15:0] n0 = in_c[15:0];
  wire signed [15:0] n1 = in_c[31:16];
  wire signed [15:0] n2 = in_c[47:32];
  wire signed [15:0] n11 = 16'sh0;
  wire signed [15:0] n12 = 16'sh1;
  wire signed [15:0] n13 = 16'sh2;
  wire signed [7:0] n14 = n2[7:0];
  wire n15 = n0 != n11;
  wire signed [15:0] n16 = 16'sh0;
  wire n17 = n1 == n16;
  wire signed [7:0] n18 = n17 ? n14 : n3;
  wire signed [15:0] n19 = 16'sh1;
  wire n20 = n1 == n19;
  wire signed [7:0] n21 = n20 ? n14 : n4;
  wire signed [15:0] n22 = 16'sh2;
  wire n23 = n1 == n22;
  wire signed [7:0] n24 = n23 ? n14 : n5;
  wire signed [15:0] n25 = 16'sh3;
  wire n26 = n1 == n25;
  wire signed [7:0] n27 = n26 ? n14 : n6;
  wire signed [15:0] n28 = 16'sh4;
  wire n29 = n1 == n28;
  wire signed [7:0] n30 = n29 ? n14 : n7;
  wire signed [15:0] n31 = 16'sh5;
  wire n32 = n1 == n31;
  wire signed [7:0] n33 = n32 ? n14 : n8;
  wire signed [15:0] n34 = 16'sh6;
  wire n35 = n1 == n34;
  wire signed [7:0] n36 = n35 ? n14 : n9;
  wire signed [15:0] n37 = 16'sh7;
  wire n38 = n1 == n37;
  wire signed [7:0] n39 = n38 ? n14 : n10;
  wire signed [7:0] n40 = n15 ? n18 : n3;
  wire signed [7:0] n41 = n15 ? n21 : n4;
  wire signed [7:0] n42 = n15 ? n24 : n5;
  wire signed [7:0] n43 = n15 ? n27 : n6;
  wire signed [7:0] n44 = n15 ? n30 : n7;
  wire signed [7:0] n45 = n15 ? n33 : n8;
  wire signed [7:0] n46 = n15 ? n36 : n9;
  wire signed [7:0] n47 = n15 ? n39 : n10;
  always @(posedge clk) begin
    if (rst) begin
      n3 <= 8'sh0;
      n4 <= 8'sh0;
      n5 <= 8'sh0;
      n6 <= 8'sh0;
      n7 <= 8'sh0;
      n8 <= 8'sh0;
      n9 <= 8'sh0;
      n10 <= 8'sh0;
    end else begin
      n3 <= n40;
      n4 <= n41;
      n5 <= n42;
      n6 <= n43;
      n7 <= n44;
      n8 <= n45;
      n9 <= n46;
      n10 <= n47;
    end
  end
  assign out_mem = {n10, n9, n8, n7, n6, n5, n4, n3};
endmodule