// detect: generated by xetal-fpga from an X_eTaL program; do not edit.
// Clocked: registers from reset, one stream item per clock.
module detect (
  input  wire clk,
  input  wire rst,
  input  wire [7:0] in_b,
  output wire [7:0] out_s,
  output wire [0:0] out_found
);
  reg signed [7:0] n11;
  reg signed [7:0] rom14 [0:7];
  initial begin
    rom14[0] = 8'sh0;
    rom14[1] = 8'sh2;
    rom14[2] = 8'sh0;
    rom14[3] = 8'sh2;
    rom14[4] = 8'sh1;
    rom14[5] = 8'sh1;
    rom14[6] = 8'sh3;
    rom14[7] = 8'sh1;
  end
  wire signed [7:0] n0 = in_b[7:0];
  wire signed [7:0] n1 = 8'sh0;
  wire signed [7:0] n2 = 8'sh2;
  wire signed [7:0] n3 = 8'sh0;
  wire signed [7:0] n4 = 8'sh2;
  wire signed [7:0] n5 = 8'sh1;
  wire signed [7:0] n6 = 8'sh1;
  wire signed [7:0] n7 = 8'sh3;
  wire signed [7:0] n8 = 8'sh1;
  wire signed [7:0] n9 = 8'sh4;
  wire signed [7:0] n10 = 8'sh3;
  wire signed [7:0] n12 = n0 * n9;
  wire signed [7:0] n13 = n11 + n12;
  wire signed [7:0] n14 = ((n13 >= 0) && (n13 < 8)) ? rom14[n13] : 8'sh0;
  wire n15 = n11 == n10;
  always @(posedge clk) begin
    if (rst) begin
      n11 <= 8'sh0;
    end else begin
      n11 <= n14;
    end
  end
  assign out_s = {n11};
  assign out_found = {n15};
endmodule