// counter: generated by xetal-fpga from an X_eTaL program; do not edit.
// Clocked: registers from reset, one stream item per clock.
module counter (
  input  wire clk,
  input  wire rst,
  input  wire [7:0] in_e,
  output wire [7:0] out_s
);
  reg signed [7:0] n1;
  wire signed [7:0] n0 = in_e[7:0];
  wire signed [7:0] n2 = n1 + n0;
  always @(posedge clk) begin
    if (rst) begin
      n1 <= 8'sh78;
    end else begin
      n1 <= n2;
    end
  end
  assign out_s = {n1};
endmodule